One useful semiconductor fabrication technique uses crystalline silicon epitaxially grown within a window through an insulator layer disposed across the face of a substrate. This epitaxially grown crystalline silicon is often referred to generically as "epi-fill". The "epi-fill" technique has been used with some success to fabricate transistors and in particular vertical bipolar transistors. For example, during the formation of the collector and base of a vertical npn bipolar transistor, a layer of oxide is deposited or grown across the face of a p-type substrate which includes a previously diffused or implanted heavily doped n-type (n+) region. The layer of oxide is then patterned and etched to open a window exposing the n-type doped region. The window is next filled with epitaxially grown n-type silicon (typically n-) to complete the formation of the collector. A p-type region is formed by diffusion or implantation into the face of the n-type "epi-fill" region and driven in under temperature to complete the base portion of the transistor. The emitter portion of the transistor can then be formed adjacent the base by either again using the "epi-fill" technique or by implantation or diffusion.
The significant drawback to the "epi-fill" process is the problem of shorting along the interface formed between the oxide layer in which the window is opened and the epitaxially grown crystalline silicon filling the window. Specifically, these shorts occur because the lack of a strong chemical bond between the insulator (oxide) and the silicon allows dopants atoms to travel along the interface, such as during implantation or diffusion of adjacent doped regions and/or during the step of thermal drive in the dopants, thereby forming a conductive region electrically coupling one conductive layer with another. In the example of the vertical npn transistor discussed above, the implantation or diffusion and thermal drive in of the base may cause the p-type dopants to extend all the way along interface between the n-type "epi-fill" and the surrounding oxide causing a short (diode) to the heavily doped (n+) portion of the base.
One means of preventing dopants from traveling along the interfaces is to mask the interfaces off at the surface during subsequent implantation/ diffusion, such as with a patterned layer of oxide. The mask however leads to dimensioning problems because part of the "epi-fill" layer is lost for use in the creation of the active device since the mask must extend over a portion of the surface the "epi-fill" to insure that the adjacent interface is completely covered. This is in addition to the fact that to form such a mask, a number of process steps, including the deposition or growth of the oxide, the deposition and patterning of the photoresist, and the etching of the oxide are required to form the mask.
The use of the of the "epi-fill" process to produce very small semiconductor devices, including bipolar and Metal Oxide Semiconductor (MOS) transistors, has further been limited by problems with planarization. The growth of the crystalline silicon through the window and beyond the plane of the oxide layer leads to a topography which is unsuitable for the fabrication of small dimension devices. In particular, with a non-planar surface, consistent definition of structure boundaries using conventional photolithographic processes becomes increasingly difficult as the device size is reduced. The varying depth of field of non-planar surface causes focusing difficulties with the photolithographic equipment which results in inconsistent and blurred pattern boundary lines. This becomes critical with small devices layouts where tolerance for errors in the photolithography is minimal.
Thus, a need has arisen for devices and methods embodying epitaxial growth ("epi-fill") techniques not subject to the disadvantages of shorting along the silicon/oxide interface and non-planar topographies.